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As the fundamental technology of autonomous vehicles and high-speed tracking, high-speed vision always suffers from the bottlenecks of on-chip bandwidth and storage due to the resource constraints. To improve the resource efficiency, we propose a hardware-efficient image compression circuit based on the vector quantization for a high-speed image sensor. In this circuit, a self-organizing map is implemented...
Artificial neural networks implement a simplified model of the human brain and thus specialize on pattern recognition. As an alternative to conventional single-instruction-multiple-data (SIMD) solutions with massive parallelism for self-organizing-map (SOM) neural network models, we report resource-efficient hardware architecture for 1-chip implementation of the learning vector quantization (LVQ)...
The developed SoC in 180nm for the implementation of a Learning Vector Quantization (LVQ) neural network is based on a concept of hardware/software co-design for on-chip learning and recognition. Minimal Euclidean distance search, which is the most time consuming operation in the competition layer of the LVQ algorithm, is solved by a pipeline with parallel p-word input architecture. Very high flexibility...
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