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In this paper we present the performance analysis of point-to-point GALS data links based on pausible clocking. The average synchronization latency and data throughput in the burst-mode communication are analytically addressed, taking the I/O port interconnect delay and the clock-tree propagation delay into account. The upper bounds for the throughput-tolerant clock tree and interconnect delays are...
Globally asynchronous locally synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant solution to address the cross-clock synchronization issues with low hardware overhead. This work explored the applications of pausible clocking scheme for area/power efficient GALS design...
In this paper we present for the first time a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating...
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