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Asynchronous circuit design has been introduced many decades ago, however until now with the limited industry application. This paper summarizes the basic asynchronous principles and techniques, as well as the latest developments as well as the outlook.
In this work, the ground bounce noise has been modeled and analyzed in frequency domain, for both synchronous and GALS (globally asynchronous, locally synchronous) systems. The analysis has been performed analytically, and validated by numerical simulations in MATLAB. Package parasitics and power distribution network have been coarsely modeled by a simple lumped model, while switching currents have...
Elliptic Curve Cryptography (ECC) represents the state-of-the-art of public-key cryptography. It is very computation intensive and hardware consuming for ASIC implementation. In this work, an ECC processor based on the Globally Asynchronous Locally Synchronous (GALS) design is presented. Attention has been paid on the resistances of GALS design against side-channel attacks (SCAs). The pausible clocking...
Digital circuits often suffer from the switching noise when synchronized by a global clock. This work investigates the spectral peak attenuation of the switching current by applying Globally Asynchronous Locally Synchronous (GALS) design. It is theoretically proven that, in particular for a plesiochronous design with M clock domains, an attenuation of up to 20logM dB can be achieved at lower order...
In this paper we present the performance analysis of point-to-point GALS data links based on pausible clocking. The average synchronization latency and data throughput in the burst-mode communication are analytically addressed, taking the I/O port interconnect delay and the clock-tree propagation delay into account. The upper bounds for the throughput-tolerant clock tree and interconnect delays are...
Globally asynchronous locally synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant solution to address the cross-clock synchronization issues with low hardware overhead. This work explored the applications of pausible clocking scheme for area/power efficient GALS design...
In this paper we present for the first time a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating...
With technology scaling into the deep sub-micron regime, the power supply and ground noise, which is introduced by the simultaneous switching activity in digital circuits, becomes a challenge for SoC and Networks-on-Chip (NoC) design. In this paper, analytical expressions of the magnitude of ground bounce for different gate switching ratios are derived. It is shown that, by spreading the switching...
With the growth in complexity of digital CMOS circuits, the steep current fluctuations introduced by numerous transistors switching with clock signals are proven to be a significant source of electromagnetic interference (EMI). In recent years the reduction in EMI noise from high speed digital ICs has already gained intensive research attention. In this paper the pausible clocking based globally asynchronous...
In this paper we introduce a novel burst-mode GALS technique. The goal of this technique is improving the performance of the GALS approach for systems with predominantly bursty data transfer. This new technique has been used to implement a GALS-based version of a hardware accelerator of a 60 GHz OFDM baseband processor. The simulation results show a significant performance improvement in comparison...
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