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The simultaneous switching activity in digital circuits challenges the design of mixed-signal SoCs. Rather than focusing on time-domain noise voltage minimization, this work optimizes switching noise in the frequency domain. A two-tier solution based on the on-chip clock scheduling is proposed. First, to cope with the switching noise at the fundamental clock frequency, which usually dominates in terms...
Mitigating switching noise in highly complex integrated circuits (ICs) is one of the challenging issues in current design flows. The common way to optimize the noise characteristics is to apply current shaping techniques, which introduce clock skew to distribute the switching activity of the circuit. However, this is typically done at late backend design stages, i.e., in layout after cell placement,...
Elliptic Curve Cryptography (ECC) represents the state-of-the-art of public-key cryptography. It is very computation intensive and hardware consuming for ASIC implementation. In this work, an ECC processor based on the Globally Asynchronous Locally Synchronous (GALS) design is presented. Attention has been paid on the resistances of GALS design against side-channel attacks (SCAs). The pausible clocking...
Globally asynchronous locally synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant solution to address the cross-clock synchronization issues with low hardware overhead. This work explored the applications of pausible clocking scheme for area/power efficient GALS design...
With the growth in complexity of digital CMOS circuits, the steep current fluctuations introduced by numerous transistors switching with clock signals are proven to be a significant source of electromagnetic interference (EMI). In recent years the reduction in EMI noise from high speed digital ICs has already gained intensive research attention. In this paper the pausible clocking based globally asynchronous...
Pausible clocking based globally-asynchronous locally-synchronous (GALS) system design has been proven a promising approach to SoCs and NoCs. In this paper, we analyze the throughput reduction and synchronization failures introduced by the widely used pausible clocking scheme, and propose an optimized scheme for higher throughput and more reliable GALS design. The local clock generator is improved...
To test timing-related faults between synchronous clocks, an at-speed test clock and an automatic test pattern generation scheme are needed. However, previous work on designing on-chip at-speed test clock controllers for multi-clock has quadratic increasing area overhead along with linearly increasing clocks. This paper presents a clock-chain based test clock control scheme using an internal phase-locked-loop...
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