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The elastic anisotropy of copper through-silicon vias (TSVs) and its impact on performance and reliability in 3-D integrated structures is examined. Copper TSVs exhibit significant amount of elastic anisotropy, particularly for TSVs with very small diameters. The elastic anisotropy manifests itself in terms of different Young's moduli in different directions and results in orientation-dependent stress...
A new methodology to bridge package and silicon domain simulations is demonstrated using a new data file to facilitate stress information exchange. The flow integration uses equivalent stress conditions to replace sensitive process information and parameterized modules to minimize user interventions for 3D IC stress simulations.
Large thermal mismatch stress can be introduced in 3D-Integration structures employing Through-Silicon-Via (TSV). The stress distribution in silicon and interconnect is affected by the via diameter and layout geometry. The TSV induced stress changes silicon mobility and ultimately alters device performance. The mobility and performance change differs in nand p- silicon and is a function of the distance...
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