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This paper proposes a novel 150-GHz single-pole-double-throw (SPDT) switch based on a rat-race coupler topology. It is designed with a 0.13-μm SiGe BiCMOS and occupies a chip area of 507 μm×542 μm. The switch achieves insertion loss of 4.0 dB/3.3 dB, isolation of 36.3 dB/35.9 dB, input return loss of 18.7 dB/12.3 dB, output return loss of 21.7 dB/26.1 dB and power-handling capabilities of 22.2 dBm/15...
In this paper, a parasitic capacitance model for a single three-dimensional (3-D) wire above a plate is developed. The model decomposes electric field into various regions and gives solutions to each part. The total capacitance is the summation of all capacitance parts corresponding to the electric field distribution. The model's physical base minimizes its complexity and error comparing to a traditional...
This paper presents a 150-GHz push-push voltage-controlled oscillator (VCO) in 0.13-μm SiGe BiCMOS process. The VCO generates the D-band output signals from 147.4 to 152.4 GHz. At 150 GHz, the simulated phase noise at 1- and 10-MHz offset frequencies are respectively −67 dBc/Hz and −93.5 dBc/Hz and the simulated output power is −21 dBm with a 50 Ω load. The VCO draws a current of 3.93 mA from a 2...
This paper presents a fully integrated 166-GHz frequency synthesizer (FS) in 0.13-μm SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler (×2) and a quadrupler (×4). The FS generates the D-band output signals from 164.08 to 166.19 GHz. At 166.19 GHz, the measured phase noises at 100-kHz and 1-MHz offset frequencies are...
This paper presents a fully integrated 166-GHz frequency synthesizer (FS) in 0.13-μm SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler (×2) and a quadrupler (×4). The FS generates the D-band output signals from 164.08 to 166.19 GHz. At 166.19 GHz, the measured phase noises at 100-kHz and 1-MHz offset frequencies are...
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