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Wireless Sensor Networks (WSN) is an important platform to build an intelligent house in the future. This paper describes a non-contact thermometer by detecting an object's radiant power. We attempt to design a portable device for remote measuring temperature, and then the device will be developed as a sensing node for WSN. A thermopile equipped with a lens was used to implement the performance. The...
Robot assisted surgery can be safer than conventional counterpart. In total knee replacement, an intelligent tool with cooperative force control equipped by the proposed bone cutting through detection is advantageous to prevent from damaging surrounding soft tissue than by conventional method or computer navigation method. In this paper the developed auto-detection bone cutting through is able to...
A practical embedded system identification approach and a frequency-domain vibration suppression control technique are developed in this study for the flexible beam driven by a permanent-magnet synchronous motor (PMSM). Simulation and experimental results indicate that the embedded system identification technique efficiently identifies the resonant frequency in velocity and positional loops, separately.
This paper presents an 8.69 Mvertices/s, 278 Mpixels/s, 15.7 mm2 tiled-based 3D graphics SoC HW/SW supporting OpenGL ES 1.0 running at 139 MHz. The SoC also includes embedded circuitry to monitor run time characteristics, detect bus protocol error/inefficiency, and capture bus traces at various abstraction levels with compression ratio up to 98%.
A tiled-based 3D graphics IP is designed to support OpenGL ES 1.0. The test chip runs at 139 MHz and achieves 8.69 Mvertices/s and 278 Mpixels/s with its die size as 15.7 mm2. The IP includes embedded circuitry to monitor run time 3DG characteristics, detect bus protocol error and inefficiency, and capture bus trace at various abstraction levels with compression ratio up to 98%.
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distributed register (DR) architecture to cope with this increasing latency. The DR architecture, though allows multicycle communication, introduces extra overhead on interconnect resource. In this paper, we propose the regular...
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