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In this paper, a 32×32-bit low power multi-precision multiplier is described, in which each building block can be either an independent smaller-precision multiplier or work in parallel to perform higher-precision operations. The proposed multi-precision multiplier enables voltage and frequency scaling for low power operation, while still maintaining full throughput. According to user's arbitrary throughput...
Low-power design is essential for computation-intensive systems such as digital signal processors (DSP) as well as battery-powered devices. This paper presents a novel low-power multiplier architecture, which exploits the effective dynamic range of the input data and performs a run-time multi-precision multiplication. Block-wise shutdown and voltage scaling techniques are combined to disable unused...
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