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This paper aims to develop an Open Verification Methodology (OVM) environment to support testing of memory protocol standards and verify their operation using coverage driven verification (CDV) and constrained random testing (CRT). The objective is to achieve most of the verification plan goals with less time and effort and to create reusable verification environment components. We demonstrate the...
In this paper, we present an Assertion based functional verification methodology for DDR type memory cores. The methodology is based on formulating DDR pattern properties extracted from JDEC standard which are then translated to synthesizable DDR Type SVA Protocol checkers for HW Emulation Platforms. The protocol checker verifies the validity of command sequences, command Timing, Mode Registers settings,...
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