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Recently, there is growing interest in directly digitizing the scintillation pulses in PET detectors. With digital pulse samples, in principle one can apply nontrivial signal analysis software algorithms to either yield better detection performance or more flexibility in detector design. Previously, we have proposed the MVT method for direct scintillation pulse sampling and developed several kinds...
Due to the high cell density, low leakage power consumption, and less vulnerability to soft errors, non-volatile memory technologies are among the most promising alternatives for replacing the traditional DRAM and SRAM technologies used in implementing main memory and caches in the modern microprocessor. However, one of the difficulties is the limited write endurance of most non-volatile memory technologies...
To alleviate the complex communication problems arising in the network-on-chip (NoC) architectures as the number of on-chip components increases, wireless network-on-chip (WiNoC) is among the most promising scalable interconnection architectures for future generation NoCs. Since 1-to-many and many-to-1 communications caused by the cache coherence protocol in the multiprocessor system have high demands...
With shrinking transistor feature size, lowering nodal capacitance and supply voltage at new technology generations, microprocessors are becoming more vulnerable to single-event upsets and transients, a.k.a., soft errors. While chip-multiprocessor (CMP) architecture has been employed in mainstream microprocessors and the number of on-chip processor cores keeps increasing, the system-level reliability...
This paper presents a mobile security SoC to deal with intensive cryptography algorithms for different security protocols. A MIPS-like general processor, a dedicated package processor for fast data package, and multiple security processors for cryptography are integrated in the SoC. Moreover, the performance can be greatly enhanced by the well-designed DTU (Data Transfer Unit), memory architecture...
This paper presents a heterogeneous multi-core SoC platform to deal with intensive cryptography algorithms in different security protocols. And several cores are integrated in the proposed Platform, which are a MlPS-like general processor (GP), a dedicated package processor (PP) for fast data package, and multiple security processors (SP) for cryptography. The low-cost dedicated SPs can execute cryptography...
Traditional mobile agent (MA) migration mechanisms focus mainly on asynchronous distributed system, and thus encapsulate the whole migration process into an inseparable action. The lack of consideration of time-space consistency makes mobile agent system (MAS) necessary to be under the control of certain high level architecture (like HLA) in distributed simulation systems (DSS). However, the scheme...
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large BTB not only dominates the predictor energy consumption, but also becomes a major roadblock in achieving faster clock frequencies at deep sub-micron technologies. In this paper, we propose a filtering scheme to reduce the...
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