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An 11b asynchronous successive approximation register analog to digital converter with embedded passive gain architecture is proposed and prototyped in 65nm CMOS. The proposed passive gain technique is integrated in the sampling capacitor network as part of the SAR conversion, and provides a signal gain of 2x prior to the comparator without consuming static current. It thus reduces the comparator...
Conversion from dc to the 10th Nyquist band is enabled in a SHA-less, 10-b, 100-MS/s pipelined ADC by digitally calibrating the clock skew in the 3.5-b front-end stage. Architectural redundancy of pipelined ADC is exploited to extract skew information from the first-stage residue output with two out-of-range comparators and some simple digital logic; a gradient-descent algorithm is used to adaptively...
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