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Reorder buffers are often needed in multi-path routing networks-on-chips (NoCs) to guarantee in-order packet delivery. However, the buffer sizes are usually over-dimensioned, due to lack of worst-case analysis, leading to unnecessary larger area overhead. Based on network calculus, we propose an analysis framework for the worst-case reorder buffer size in multi-path minimal routing NoCs. Experiments...
The susceptibility of digital systems to single event transients becomes increasingly severe with CMOS technology scaling, and transient faults analysis becomes more and more important. As technology scales further in sub 40 nm, process variations present another major design challenge, which makes the transient faults analysis more complicated. To address process variations, this paper presents a...
Variability from different sources such as layout-dependent effects due to strain has been a main obstacle against aggressive design rules and reducing corner margins in 32nm node and beyond. This paper reports and demonstrates a model development and verification platform to accurately address layout dependences due to strain. This platform has been successfully used in real design exercises at 40nm...
In this paper, limit cycle which results from friction during low-velocity servo system has been discussed. First, the piecewise linearization method has been applied to change nonlinear stribeck model to linear model. Second, with analysis of equilibrium property, it is proved the existence of limit cycle and its certain region. The analysis reveals that it is because of stability of equilibrium...
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