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In this paper, we propose a high-speed parallel GF(2128) bit multiplier for Ghash function in conjunction with its FPGA implementation. Through the use of Verilog the designs are evaluated by using Xilinx Vertax5 with 65 nm technic and 30,000 logic cells. The highest throughput of 30.764 Gpbs can be achieved on Virtex5 with the consumption of 8864 slices LUT. The proposed design of the multiplier...
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