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A new sidewall interconnection approach using a perpendicular circuit die is implemented in this paper; this device can be applied to the fabrication of chip stacks. Thermal stress analysis is implemented using the ABAQUS software package to investigate the reliability issues of a stacked chip. The analysis indicates that it has little effect on the reliability of the stacked chip. Experiments were...
A new sidewall interconnection using perpendicular circuit die is implemented in this work; this device can be applied to fabrication of chip stacks. Experiments were conducted by stacking four chips each having a thickness of 200μm; the configuration of the pad on the test chip is similar to that of a memory chip. The chips for stacking were fabricated successfully by dicing the wafer. Vertical interconnection...
An edge traces technique in the wafer level is proposed and implemented in this work, which can be applied to the fabrication of the stack chip. Experiments were conducted by stacking four test chips 100μm thick, and the configuration of the pad is based on the memory chip from the electronics company. The chips for stacking were fabricated successfully through dicing the wafer and curing the adhesives...
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