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In this paper we investigated the compressive stress in the channel induced by shallow trench isolation (STI) for different active length (Sa). We simulate both PMOS and NMOS for 130 nm gate length with five active lengths (Sa=0.34, 0.5, 0.8,1.0, 5.0 um) by using TCAD simulation and compare to experimental data from wafers fabricated using Silterra's 130 nm Technology. When the Sa is decreasing, Sxx...
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