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This paper presents the impact of FDSOI back gate biasing on circuit conducted emission. The back gate bias can modulate front gate electrical characteristic, and changing the circuit performance and power consumptions dynamically. Meanwhile, the electromagnetic emission of circuit is changing with the back gate variation. A ring oscillator is tested to illustrate the relation between back gate biasing...
Firstly an embedded 55-nm Flash design based on split-gate Flash bitcell is proposed by 32KX64 IP. It demonstrates competitive features for production by wide voltage supply range (VDD=0.86~1.32V, and VD25=1.6~3.6V), low-power read feature (96uA/MHz, 64 bits), fast wake-up time from power off (<; 2us), and fast operation read speed up to 75MHz (VDD=1.08V).
Analog circuits such as linear voltage regulators are very sensitive to electromagnetic interferences which induce voltage offset on their outputs. In harsh environments, the aging of this component can be accelerated and could lead to an increase of the effect of electromagnetic interferences. This paper proposes an original study about the drift of the susceptibility level of a low dropout voltage...
This paper presents a new technique which combines variable-threshold (VT) keeper with split-domino (SD) logic technique to improve the power performance. The proposed technique yields 9-14% energy reduction, with 10% area overhead. We will compare the proposed method with the-state-of-the art for reducing leakage current in domino logic circuits. A 16-bit multiplexer circuit, in 0.13 mum CMOS technology...
In this paper, we compare different existing keeper techniques for reducing power consumption of wide domino logic circuits. We will compare power consumption plus area overhead of each of these methods, with the conventional keeper circuit. A 16-bit multiplexer circuit, in 0.13 mum CMOS technology operating at a frequency of 500 MHz is our test-bench. Simulations show split-domino (SD), with 53%...
A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complimented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time...
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