The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this paper, an X-tree clock distribution topology based on standing wave oscillator is introduced. To increase output amplitude at the loading point and saving chip area, a novel CMOS active inductor is designed and applied to each loading points of the network. The cascoded differential active inductor is 1 nH with Q = 344 at 10 GHz. This makes the two stage, 6.2 mm × 6.2 mm dimensional standing...
Mechanical vibration energy is widespread in nature. Lots of research shows that the inverse effect of the magnetic shape memory alloys (MSMA) can be fully used to convert the vibration energy in nature into electrical energy, to achieve the power supply of the sensor and the lithium battery. In order to acquire the accuracy of simulate of the MSMA, the signal generated by MSMA need to be transformed...
Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of...
This paper presents a CMOS neuron circuit design based on the Hindermarsh-Rose (HR) neuron model. In order to be fabricated in a 0.18μm CMOS technology with 1.8V compatible transistors, both time and amplitude scaling of HR neuron model is adopted. This on chip solution also minimizes the power consumption and circuit size, which is ideal for motion control unit of the proposed bio-mimetic micro-robot...
This paper presents a low power circuit design for an electronic nervous system composed of central pattern generator (CPG) to control a biomimetic robot that mimics the lamprey swimming system. The circuit has been designed using 65nm CMOS technology model at 0.8V supply. The design challenges of narrow voltage design margin and high sensitivity to parameter variation are addressed by circuit optimization...
Accurate peak power measurement requires detailed switching and delay information for each signal over the entire simulation. Performing a full signal dump and power calculation for a long simulation run usually spends a large amount of time and disk space. In this paper, we propose an Essential-signal-based methodology which only performs power analysis over a small subset of the original simulation...
The fault diagnosis has become an increasing portion of todaypsilas IC-design cycle and significantly determines productpsilas time-to-market. However, the failure behaviors from the defective chips may not be fully represented by the single fault model. In this paper, we propose a fault-diagnosis framework targeting multiple stuck-at faults. This framework first reports a minimal suspect region,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.