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We report the first demonstration of III-V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process which is compatible with CMOS process flow. A new epitaxy process was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. Nickel was deposited and annealed to...
We report the first demonstration of a self-aligned contact technology for III-V MOSFETs. A novel epitaxy process with in-situ surface treatment was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. By precisely and fully converting the GeSi layer into NiGeSi, while diffusing Ge and Si into GaAs to form heavily...
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 ?? ?? ?? 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n+-Ge1-xSix/p-Ge1-xSix is compared with n+-Ge/p-Ge. These results indicate...
A reference circuit employing sub-threshold current is presented, which uses two CTAT currents and resistor temperature compensation to generate a reference voltage of 200 mV. Since most of MOSFETs are working at sub-threshold region, the circuit only consumes 716 nW at supply voltage of 1 V with PSRR of -53.5dB at room temperature using TSMC 0.18 mum technology. The reference voltage's average temperature...
High source/drain concentration level, ultrashallow junction, and high-mobility channel are important for the requirements of nanoscale transistors. Microwave processing of semiconductors could offer distinct advantages over conventional RTP systems in some applications, and the anneal temperature is within the range of 300degC-500degC. By using a low-temperature microwave anneal, the sheet resistance...
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