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A 10b 150MS/s 0.4mm2 pipeline ADC is implemented in a 45nm CMOS process. The input SHA, employing four charge-redistributed capacitors, converts single-ended or differential input signals of 1.2Vpp to differential outputs of 0.8Vpp for a low supply voltage of 1.1V. The process-insensitive high-gain amplifiers in the SHA and MDACs are based on gain-boosting, pseudo-differential output pair, and continuous-time...
This work proposes a 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC optimizing power consumption and chip area for analog TV (NTSC/PAL) applications. The proposed DAC employs a 2-step (6b-4b) split-capacitor array with the VCM-based switching method for high power efficiency and small chip area. Additionally, a range-scaling technique is employed for a rail-to-rail input signal swing. The comparator accuracy...
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