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A passive UHF RFID tag's baseband processor design with energy-aware structure is presented in this paper, based on EPC C1G2 protocol. For the consideration of limited availability of power and low-voltage supply, ripple-binary mixed counter and compensated addition are proposed for the PIE decoder. And in the clock generator for tag-to-reader uplink, Galoi linear feedback shift register (LFSR) is...
In this paper, a low-power signal processing front-end and PIE decoder for use in UHF RFID passive transponders is presented. By merging with the decoder, the clock generator does not need to drive a large loading capacitor. Therefore, its power consumption can be greatly reduced. In addition, the ring oscillator of the generator was designed for low sensitivity to supply voltage variation and low...
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