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In this paper, we propose a 2-D grouping FIFO based FFT hardware architecture, supporting 36 different FFT sizes defined in 3GPP-LTE systems. Also, the important design foundation is to develop a hybrid-radix computing kernel engine, including 4 configuration types. In a design implementation via TSMC 90-nm CMOS technology, the reconfigurable FFT chip only has a core area occupation of 1.51 mm2, dissipating...
In this paper, we propose a cost-efficient hardware design, coarse and fine rotation (CFR) based FFT twiddle factor generator. It aims to extremely reduce the hardware area, especially for the larger length of FFT-points. Also, our proposed approach is generalized for arbitrary FFT sizes, not limited to the power of 2. In hardware implementation by using TSMC 90-nm CMOS technology, the circuit area...
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