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This paper presents a dual-mode intermediate frequency (IF) signal processing circuit for pulse compression radar (PCR) and symbol recovery. A half-duplex architecture is proposed to support modulation and demodulation of PCR signals. For data communication, the modulator and the demodulator support up to 3-Gb/s QPSK signal. For range sensing, the proposed IF correlation technique supports 1.5-GHz...
This paper presents a reconfigurable analog signal processing circuit for pulse compression radar. Adapting bandwidth for the range of the target is proposed for radar systems. The baseband signal processor includes a high-speed correlator/integrator, a 4-bit flash analog-to-digital converter (ADC) and a multi-range delay lock loop (DLL). The DLL generates multi-phase clock to align the template signal...
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