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This paper presents a model checking-based schedulability checking approach for Rate-Monotonic Scheduling (RMS) algorithm. To do so, RMS algorithm is modelled with TMSVL, and the desired property, i.e. Schedulability, is specified with the property specification language in TMSVL. Next, whether RMS algorithm is schedulable on a set of tasks is verified by checking whether the desired property is valid...
Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadline-constrained...
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