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This live demonstration is related to ISCAS track “Imagers and Vision Processing”. It showcases the Gaussian pyramid with a CMOS vision sensor with a 176 × 120 pixel array in standard 0.18 μm CMOS technology. The sensing elements are 3T-APS with in-pixel ADC and CDS. The Gaussian pyramid is extracted concurrently with a double-Euler switched-capacitor network on the same substrate, giving RMSE errors...
The optical characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. The overall full-width half-maximum (FWHM) of the detector ensemble SPAD plus TDC is 690ps. The sensor has been fabricated in a 0.18μm standard CMOS technology which features an average dark-count rate (DCR) of 42kHz at 1V excess voltage (Ve) and room...
The design and characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. It is targeted for time-resolved imaging, in particular 3D imaging. The achieved pixel pitch is 64μm with a fill factor of 3.5%. The chip was fabricated in a 0.18μm standard CMOS technology and implements a double functionality: Time-of-Flight estimation...
The design and simulation of a CMOS 8 × 8 single photon avalanche diode (SPAD) array is presented. The chip has been fabricated in a 0.18μm standard CMOS technology and implements a double functionality: measuring the Time-of-Flight with the help of a pulsed light source; or computing focal-plane statistics in biomedical imaging applications based on a concentrated light-spot. The incorporation of...
This paper describes a 1-D Focal Plane Processor incorporating 200 pixels for Continuous-Time Optical Correlation Applications. Each pixel incorporates a 2 mm times 10.9 mum photodiode whose current is scaled, at the pixel level, by 5 independent 3-bit programmable-gain current amplifiers. Correlation patterns, defined as 5 sets of 200 3-bits numbers, are communicated to the chip via a standard I2...
A novel concept is presented for the generation of truly random signals for analog/digital VLSI circuits. It is based on the analog implementation of very simple chaotic discrete-time systems. This concept is demonstrated via two monolithic Switched-Capacitor CMOS prototypes (respectively in a 2??m doublemetal single-poly technology and in a 3??m double-metal double-poly one). Both analog and digital...
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