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A versatile low-cost manufacturing technology, which is based on the optimum variation lateral doping technique, is proposed for smart power ICs in this paper. The proposed technology is capable to combine the lateral and vertical high voltage (> 800V) devices on a single chip, which is suitable for applications over broad current ranges. It is fully compatible with BiCMOS process and has been...
This paper developed a forward body-bias technique to reduce the power consumption of a low power and compact size low noise amplifier (LNA) in tsmcTM 0.18 µm CMOS technology. The LNA can operate at very low power consumption of 4.9 mW from a 0.7-V supply voltage. The proposed LNA achieves a gain of 11 dB and an input IP3 of −7.5 dBm at 25 GHz. The operating bandwidth is from 24 to 26.5 GHz. The chip...
Degradation of electrical characteristics of NdAlO3/SiO2 stack gate under the constant voltage stress (CVS) is presented. It is found that the electron trapping, positive charges and oxide trap generation acts together, which causes the degradation of NdAlO3/SiO2 stack gate. The transport mechanisms of the gate leakage current in NdAlO3/SiO2 stack gate are also investigated. Frenkel-Poole emission...
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