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Current practices for the design and deployment of hardware redundancy techniques in embedded systems remain in practice specific (defined on a case-per-case basis) and mostly manual. This paper addresses the challenging problems of engineering fault tolerance mechanisms in a generic way and providing suitable tools for coping with their deployment. This approach relies on metaprogramming to specify...
The selection of IP cores for integration in hardware systems requires the evaluation, comparison and ranking of all eligible core candidates. In this context, the development of suitable benchmarking techniques to balance the different performance, dependability, area and energy consumption measures is an essential, but also a challenging task. This paper specifies a benchmarking approach that exploits...
Hardware fault tolerance is a requirement even for noncritical applications, since unexpected failures may damage the reputation of manufacturers and limit the acceptance of their products. However, current practices for the design and deployment of hardware redundancy techniques remain in practice specific (defined on a case-per-case basis) and mostly manual. This paper addresses the challenging...
Many designers bet on reducing time-to-market costs by integrating off-the-shelf (OTS) cores in their embedded solutions, while looking after maintaining the confidence placed by users in their products. Balancing these aspects is challenging and claims for suitable techniques to select, among eligible candidates, those exhibiting adequate levels of dependability. Thus, the early and efficient dependability...
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