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FPGA-based time-to-digital converters provide a relatively low cost and flexible solution to test and measurement applications. However, the choice of time-to-digital conversion techniques is limited by the FPGA architecture, and the measurement resolution and accuracy suffer from inevitable intra-FPGA variations. In this paper, we propose a multi-channel time-todigital conversion technique. The basic...
In this paper, a bit weight extraction technique is proposed to test and calibrate the successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique is based on major carrier transition (MCT) testing, the MCTs are generated through simple capacitor switching and then measured by the embedded comparator and a coarse design-for-test (DfT) digital-to-analog converter...
Capacitor mismatch is the linearity limiter of charge redistribution SAR ADCs. This paper aims at detecting and removing the mismatch induced missing-decision levels (MDLs), i.e., large positive DNLs; these errors lead to information loss that cannot be recovered by external calibration. A switched-capacitor based approach is proposed to avoid DC currents and reduce design overhead; the hardware modification...
This paper presents pre/post-bond testing and calibration techniques for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The underlying idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of its digital-to-analog converter (DAC) capacitor array (C-Array). During the pre-bond stage,...
This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4...
Loopback testing is a powerful technique for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) pair embedded in a mixed-signal system-on-chip (SoC). While attractive, its performance is generally limited by the achievable test resolution and the potential fault masking problem. In this work, a loopback linearity testing technique for an ADC/DAC pair is presented;...
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