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FPGA-based time-to-digital converters provide a relatively low cost and flexible solution to test and measurement applications. However, the choice of time-to-digital conversion techniques is limited by the FPGA architecture, and the measurement resolution and accuracy suffer from inevitable intra-FPGA variations. In this paper, we propose a multi-channel time-todigital conversion technique. The basic...
The programmable delay line is one of the key components in automatic test equipment. Recently, implementation of programmable delay lines on FPGAs has drawn growing attention due to the flexibility and reconfiguration capability that FPGAs provide. In this work, we propose the subset sum delay line (SSDL) architecture for FPGA-based delay lines. The SSDL architecture takes advantage of the inevitable...
The programmable delay line is a key component in test and measurement applications; it facilitates key functionalities such as de-skewing, timing adjustment, edge placement, and time-to-digital conversions. In this work, we investigate the implementation of programmable delay lines on off-the-shelf FPGAs (field programmable gate array). Two flavors of delay lines, coarse and fine, are realized and...
Identifying speed-limiting paths is crucial for design stepping in which problematic paths are fixed or optimized so as to reach higher clock rates. Recently, using at-speed scan test patterns to identify speed-limiting paths has been reported to be a robust and effective solution. In this paper, we propose a systematic approach to find suspect path expressions (SPE) that explain the observed failing...
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