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Modular multilevel converter (MMC) is a promising topology of Voltage Source Converter based High voltage Direct Current (VSC-HVDC) system with many outstanding advantages such as low switching frequency, low voltage distortion and harmonics. Pre-charge process is one of the core issues of MMC based system, especially for the MMC with DC fault blocking capability. In this paper, considering a novel...
The modular multilevel converter (MMC) is a competitive candidate for VSC-HVDC systems. However, the conventional HB-MMC can't block dc link fault current because of the freewheeling effect of diodes. To solve this problem, researchers proposed an account of sub-modules (SMs) with DC-fault current clearing capability. This paper summarizes the 2 basic criteria and provides a comprehensive review of...
The modular multilevel converter (MMC) is a competitive candidate for medium/high-power applications, specifically for high-voltage direct current transmission systems. Model predictive control (MPC) is an advanced and flexible method for power converters. The existing MPC methods for the MMC 3-phase system treat whole system as a three independent single phase system, and the computational load increases...
This paper focuses on the electromagnetic interference (EMI) research and analysis of the MHz switching frequency GaN MOSFET based on the LLC resonant DC-DC converter. In this paper, first, the CM coupling paths are studied to get simplified models. Then the impact of the parasitic capacitors (both the capacitors to the ground and the capacitors in the devices) on the CM current are analyzed. Finally...
In this paper, a bit weight extraction technique is proposed to test and calibrate the successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique is based on major carrier transition (MCT) testing, the MCTs are generated through simple capacitor switching and then measured by the embedded comparator and a coarse design-for-test (DfT) digital-to-analog converter...
Capacitor mismatch is the linearity limiter of charge redistribution SAR ADCs. This paper aims at detecting and removing the mismatch induced missing-decision levels (MDLs), i.e., large positive DNLs; these errors lead to information loss that cannot be recovered by external calibration. A switched-capacitor based approach is proposed to avoid DC currents and reduce design overhead; the hardware modification...
This paper presents pre/post-bond testing and calibration techniques for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The underlying idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of its digital-to-analog converter (DAC) capacitor array (C-Array). During the pre-bond stage,...
This paper utilizes the Field-Programmable-Analog-Array (FPAA) platform to implement a low-cost design-for-test technique that characterizes the leakage factor of a switched-capacitor (SC) integrator. The maximum leakage measurement error is 1.89%.
This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4...
This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator...
For embedded analog-to-digital converters (ADCs) fabricated with deep sub-micron technology, calibration has become mandatory to ensure acceptable yield against process variations. This paper presents a pipelined ADC calibration technique that targets the capacitor mismatch and comparator offset associated with the pipelined ADC stages. The calibration technique is self-testing assisted; it utilizes...
In this paper, we present a histogram-based two-phase calibration technique for capacitor mismatch and comparator offset of 1-bit/stage pipelined Analog-to-Digital Converters (ADCs). In the first phase, it calibrates the missing decision levels by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing...
In this paper, we present an efficient calibration technique for 1-bit/stage pipelined analog-to-digital converters (ADCs). The proposed technique calibrates capacitor mismatch and comparator offset induced non-ideal ADC output behavior; it is a two-phase calibration scheme that relies on linear histogram testing to collect the required information. In the first phase, it calibrates the missing-decision-level...
For modern display systems, thorough testing of the TFT array is a critical element in yield management. However, for system-on-panel displays which integrate drivers, timing units, and controllers on the same substrate (usually glass) as the TFT array, access to the array data and scan lines is complicated. To reduce the tester complexity, we propose a low area overhead and offset compensated charge...
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