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The excessive circuit switching activity during scan-based at-speed testing has been known to cause yield loss because it degrades the circuit performance and can cause a good device to fail the test. In this paper, we propose an IR-drop aware test pattern generator to produce high-quality at-speed test patterns. The idea is to manage the switching activity distribution of the generated test patterns...
This work proposes a power supply noise reduction technique for at-speed testing in the broadcast-based test compression environment. The core technology is the X-slice creation technique, it comprises the scan-chain skew-insertion hardware and the skew configuration generation algorithm. With the created X-slices, the efficiency of X-slice filling to lower the launch cycle switching activity is improved...
This paper presents PHS-Fill, an ATPG technique that reduces(1) power supply noise for scan-based at-speed testing, and(2) test data volume in a Huffman coding based test compression environment. PHS-Fill first identifies the preferred Huffman symbols; these symbols correspond to the test pattern templates that improve test compression and reduces power supply noise at the same time. ATPG then biases...
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