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This work analyses ultra-shallow pFET junctions in 330nm-thin germanium virtual substrates, selectively grown in the active regions of Shallow Trench Isolation (STI) patterned silicon wafers. The area leakage is 5–10 times higher than similar junctions in thick Ge virtual substrates if a Post-Growth (PG) anneal is done to reduce the density of threading dislocations. On the other hand, there is a...
This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330nm) Ge epitaxial layers, selectively grown in Shallow-Trench Isolation (STI)-patterned wafers are presented. These thin layers show a 70% higher area junction leakage than thick Ge virtual substrates at 1V bias, but the presence of STI reduces the leakage at the isolation perimeter by a factor of 5.Low-temperature...
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