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This paper describes two encryption designs of Chinese wireless local area network block cipher standard - SMS4 algorithm. Then these two designs are implemented on Xilinx Virtex-4 FPGA devices. The first (pipelined) design is optimized in order to reduce time delay and the encryption core has a throughput of 24 Gb/s. The second (folded) design is optimized in order to minimize area coverage and the...
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