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We have experimentally analyzed the leakage mechanism by comparing the planar DRAM cell and the recently developed DRAM cell transistors that have deeply recessed channels. We have identified important differences in the leakage mechanisms between planar MOSFETs and recessed channel MOSFETs, so we can suggest guidelines with respect to the optimal device structures for the recessed channel DRAM cell.
We have experimentally analyzed the leakage mechanism and device degradations caused by the F-N and hot carrier stresses for the recently developed DRAM cell transistors having deeply recessed channels. We have found the important difference of the leakage mechanism between S-Fin and RCAT, which have each structural benefit in the characteristics of leakage current, so we can suggest the guide lines...
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