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Existing silicon validation techniques only address test data capture issues. They all assume the existence of live traffic in the system. Unfortunately, this is not always the case in real life. This paper proposes a novel design methodology for silicon validation and system integration. It uses built-in functional tests to simulate live traffic at full speed when a real one is not available at the...
An SoC ASIC is an integration of many complex components such as analog cores, digital cores, user defined logic, memories, etc. If not properly planed, lab validation of such an ASIC can be time consuming. This paper proposes a design for validation architecture that includes a built-in functional test for fast lab validation and system integration. The proposed scheme has been adopted in a 40 Gbps...
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