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We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction...
We have developed a novel junction profile engineering using laser spike annealing (LSA) with co-implant and applied it to sub-30-nm strained CMOS devices. A 55% reduction in source-drain extension (SDE) resistance achieves a 15% improvement in the saturation on-current (I on) at a 28-nm gate length for PMOS. A reduction in the source-dram parasitic resistance enables an over 50% improvement in the...
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