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Two models for the analysis of races in asynchronous sequential networks constructed with gates are described. The first model is a modification and a formalization of intuitively clear concepts. The second model is applicable, if the delays associated with the gates do not differ too widely from each other. A new concept of internal state is required in this model; namely, in addition to the values...
The family of G-trivial languages is investigated. This family is a generalization of L-trivial and R-trivial languages, a relationship analogous to the one between generalized definite languages and the definite and reverse definite languages. Characterizations of G-trivial languages are given in terms of their syntactic monoids, various congruence relations, and the (finite) automata which recognize...
Ternary simulation techniques provide efficient methods for the analysis of the behavior of VLSI circuits. However, the results of ternary simulation have not been completely characterized. In this paper we outline the proof of the Brzozowski-Yoeli conjecture (stated in 1976) that the results of the ternary simulation of a gate network N correspond to the results of the binary race analysis of Ñ in...
We survey three applications that use finite automata to specify behaviors of concurrent processes in general, and asynchronous circuits in particular. The applications are: verification of concurrent processes, liveness properties, and delay-insensitivity of asynchronous networks. In all three cases, we start with a common model of a nondeterministic finite automaton, and then add certain application-specific...
We develop mathematical switch-level models for static combinational CMOS networks. In contrast to other available MOS models and theories, our models capture design principles that are special to CMOS, such as the use of transmission gates. First we study networks consisting of cascade connections of CMOS cells realizing negative functions. We then extend this model to incorporate transmission gates...
Some recent developments in the design of asynchronous circuits are surveyed. The design process is considered in two parts. First, the communication behaviour of the component to be designed is formally specified and this specification is decomposed into a network of basic components. Second, the basic components are realized using gate circuits. In the first part of the design process we...
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