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This paper presents a 60GHz direct-conversion transceiver using 60GHz quadrature oscillators. The 65nm CMOS transceiver realizes the IEEE802.15.3c full-rate wireless communication for every 16QAM/8PSK/QPSK/BPSK mode. The maximum data rates with an antenna built in the package are 8Gb/s in QPSK mode and 11 Gb/s in 16QAM mode within a BER of <;1CH, and the transmitter and the receiver consume 186mW...
This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled with a frequency tripler to generate the 60GHz signal. Both the 20GHz PLL and the ILO were fabricated using a 65nm CMOS process and measurement results...
This paper presents a LC-based sub-harmonic injection-locked frequency quadrupler which multiplies a 15 GHz input to 60 GHz quadrature(I/Q) output signals. The proposed quadrupler can use a lower-frequency PLL for incident signal than doublers and triplers, which is very advantageous to implement a wide-tuning and low-phase-noise PLL. The proposed frequency quadrupler is implemented by using a 65...
In this paper we present a statistical analysis method which bridges the statistical information between process-level and system-level. This enables us to evaluate the effect of process variation at the system level. Also, we can derive constraints on the process variation from a performance requirement. We show an example of the hierarchical statistical analysis applied to a Phase Locked Loop (PLL)...
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