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The new packaging approach for crystal resonator with quartz crystal is described in this paper. We designed and optimized the structure of wafer level crystal unit package for low cost and high performance with 2.0??1.6??0.45 mm3 size. The crystal unit package is reduced in size and thickness by using a 4" wafer level package technique of general semiconductor process. Traditionally, the package...
Most important technology for developing of wafer level packaging is studied in this paper. That is the process of drilling the via hole that are needed filling of conductive material for electrical connection or non-conductive material for reliability. Several kinds of drilling and filling methods of via holes for the interconnection were studied. The via formation for interconnection is based on...
In order to develop high density NAND flash device, the increased number of cell strings for 1 page buffer forces to form a long bit-line with low sheet resistance, as well as low parasitic capacitance between bit-lines. In this paper, we secured a copper damascene process to form 38 nm bit-lines with 76 nm pitch using SADP (self-aligned double patterning) process. The methods to minimize the sheet...
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