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The inverted dependence of the soft-error rate (SER) on the cycle time in static RAMs with high resistive load cells is described. The inverted dependence is observed in the SRAM with a PMOS bit-line load. At a cycle time of 100 ns, the SER is reduced by 1.5 orders of magnitude, compared with that of the SRAM with NMOS bit-line load. The mechanism is explained with reference to the time constant of...
An 8-ns serial access time has been realized in a 4-Mb static RAM with newly proposed circuits (hierarchical shift registers and look-ahead circuits) which can access up to 4 Mb. This memory realizes a 125-MHz fast serial READ/WRITE operation suitable for ultra-high-speed memory systems such as image-processing systems, high-speed testing systems, and supercomputers. This function is also beneficial...
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