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This paper studies the problem of coverage management with two emerging formalisms in simulation based validation, namely formal specification of test points and the use of inline temporal assertions. We present methods for checking whether a test-bench with inline assertion covers a set of formal test points. This is particularly useful in developing verification IPs for standard on-chip protocols...
The scope of immediate assertions in SystemVerilog is restricted to Boolean properties, where as temporal properties are specified as concurrent assertions. Concurrent assertion statements can also be embedded in a procedural block - known as procedural concurrent assertions which are used under restricted situations. This paper introduces the notion of inline assertions which generalizes the embedding...
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