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We present a fully cell-based All-Digital Phase-Locked Loop (ADPLL) with almost continuous tracking range of frequency. Using TSMC 0.18μm CMOS technology, this test chip can operate from 91.6MHz to 1.173GHz with an average resolution of 2.1ps. It features a new Mirror-DCO-Based Calibration Mechanism that enables smooth code-jumping to mitigate the segmented clock-period profile problem faced by most...
In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter by a number of schemes. First, the phase is locked quickly through a predictive phase-locking scheme. Then, the jitter is further reduced by a suppressive digital loop filter. Finally, an interpolation-based locking scheme is utilized to enhance the resolution of...
In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1 ps resolution. Combined with a programmable divider with multiplicative factor from 1 to 2046, various frequencies could be synthesized to meet different applications. In order to reduce output clock jitter after phase...
In this paper we present a high-resolution and wide-range all-digital phase-locked loop (ADPLL), which is suitable to function as a clock generator. The digitally controlled oscillator (DCO) is able to operate from 70 to 725 MHz and achieves 5.2ps resolution. The phase-frequency detector (PFD) is designed using a latch-based sense amplifier, leading to a nearly perfect PFD that is able to resolve...
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