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We present a fully cell-based All-Digital Phase-Locked Loop (ADPLL) with almost continuous tracking range of frequency. Using TSMC 0.18μm CMOS technology, this test chip can operate from 91.6MHz to 1.173GHz with an average resolution of 2.1ps. It features a new Mirror-DCO-Based Calibration Mechanism that enables smooth code-jumping to mitigate the segmented clock-period profile problem faced by most...
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