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The study in this paper is to solve the compatibility of the PLB and AHB interface. In our FPGA hardware platform, we use the PowerPC embedded in Xilinx Virtex4 as our CPU, which follows the PLB protocol. As our slave IP cores are all designed with the AHB interface, we need to design a PLB-AHB bridge to translate the two protocols. This paper describes in detail the designing of such a bridge, which...
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