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A multi-bit Delta-Sigma ADC employing a nonlinearity suppressed feedback DAC is presented in this paper. Methodologies for a mismatch-insensitive design are proposed and investigated. Measurement results from prototypes fabricated in a 0.13μm process demonstrate that without dynamic-element-matching or calibration techniques, the Delta-Sigma modulator employing a 7-level feedback DAC achieves a SFDR...
Linearity analysis of a calorimetric thermal voltage converter (CTVC) designed by the National Research Council of Canada for RF-DC transfer difference up to 1 GHz is presented in this paper. At higher frequencies, the CTVC is evaluated in terms of the calibration factor of a RF power sensor and the reflection coefficients at its Type-N connector. Good performance has been observed which indicates...
A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gain-boosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level...
A 3-bit 3rd-order Sigma-Delta modulator employing a switched-capacitor multiply-by-N DAC is described in this paper. The DAC is implemented in a capacitor mismatch independent way to improve circuit linearity. Theoretical analysis on the effect of finite op amp DC gain on DAC linearity is given. A prototype Sigma-Delta modulator for verification purpose was built with discrete components on printed...
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