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The Fibonacci Switched-Capacitor (SC) converter demonstrates the highest performance by using minimum number of capacitors. However, as the Fibonacci SC requires a wide range of voltage rating of the devices, its implementation is difficult. This paper presents two gate driving techniques for designing and implementing two-phase Fibonacci SC converter for both low and high step-up conversion ratios...
The development of charge pumps has been motivated by the power supply requirements of portable electronic devices. Charge pumps are inductorless DC-DC converters that are small size and high integration. The quality of the charge pump greatly depends on the effectiveness of switches to turn on and off at the designated clock phases. However, to date, no analysis has been carried out on the overall...
This paper presents a three-dimensional cellular genetic algorithm (3D-cGA) to achieve fault tolerance; in particular, faults occurred due to single event upsets (SEUs). Cellular genetic algorithms (cGAs) are targeted due to their high performance and inherent features, among others. Genetic diversity is the main factor in identifying and isolating faults occurred, particularly at individuals' phenotypes...
In this paper we propose a new algorithmic approach to achieve fault tolerance based on three dimensional cellular genetic algorithms (3D-cGAs). Herein, 3D architecture is targeted due to its amenability to implementation with current advanced custom silicon chip technology. The proposed approach is designed to exploit the inherent features of a cGA in which the genetic diversity is used as the key...
This paper aims to compare the effect of dynamically controlling the exploration-exploitation trade-off in cellular Genetic Algorithms (cGAs) from two perspectives: first, through lattice reconfiguration while dynamically changing the grid-neighbourhood ratio and thus taking advantage of their inherent structural properties; second, through local selection using a recently developed method known as...
Pre-fetching in a memory hierarchy is known to alleviate the “memory wall” paradigm but its use is impeded because of the difficulty to estimate efficiency when used in a complex system such as a SoC (System on Chip) or NoC (Network on Chip). Therefore, some methods are needed to evaluate the benefit of pre-fetching at the earliest possible stage in a design flow to help the designer choose architectural...
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