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WK-recursive based networks well conform to a modular design due to the properties of regularity and scalability. Here, the focus is on a triplet-based WK-recursive topology and its implementation using tiled shapes in multi-core processors design is explored. To further improve the network throughput and reduce the network latency, a pair of heterogeneous topologies is proposed to separate the core...
Network-on-Chip (NoC) Router has an important impact on the network communication performance. High performance router will help to build a high-throughput, power-efficient and low-latency NoC. However, the existing baseline router of Triplet-based Hierarchical Interconnection Network (THIN) can not fully exert the potential performance of THIN because it does not consider the characteristic of THIN...
Object-oriented (OO) programming appears as a promising framework for parallel programming. Objects which are inherently concurrent communicate through message passing. But most of OO languages choose to avoid supporting message passing directly because the implementation is too complicated. As we enter the era of CMP with multiple cores on a single die, real message passing can be realized. Objects...
Data switch structure is necessary to support data transfers in network on chip (NoC). Most of designs can only support one-direction data transfer, and the potential concurrency is omitted. Concurrent multi-direction data switch structure (CMDSS) that proposed before can offer several concurrent transfers. In this paper, graph theory is used to help designing the structures, and the method is called...
A new chip design paradigm called Network-on-Chip (NOC) offers a promising architectural choice for future SOC (System-on-Chip). Triple-based Hierarchical Interconnection Network (THIN) was proposed that aims to decrease the node degree, reduce the links and shorten the diameter. The topology of THIN is very simple and it has obviously hierarchical, symmetric and scalable characteristic. In this paper,...
On-chip communication architectures can have a great influence on the speed and area of multi-core processor (MCP) designs. A new chip design paradigm called network-on-chip (NOC) offers a promising interconnection architectural choice for future MCP. A new on-chip interconnection network named Triple-based Hierarchical Interconnection Network (THIN) is proposed that aims to decrease the node degree,...
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