The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper puts forward a comparison between two 1 bit full adder designs: one using 4T XOR and the other using 4:1 MUX based 3 Input XOR. Both are designs are made up of 10 transistors. The simulation is done using Cadence Simulator at 180nm and 90nm Technology. Comparison is made among the two proposed designs with respect to power and delay. The results show the efficiency of the design.
This paper puts forward a novel 4T 2∶1 mux design. The circuit is designed using 2 nmos transistors and an inverter. The design is done using DSCH 2.6 tool. Simulation and power calculation is done at different levels of technology using Microwind 2 Simulator. Comparison is done with the traditional TG (transmission gate) 2∶1 mux design. The results show the efficiency of the design.
This paper puts forward a comparison among few different 2:1 mux designs: 2T, 4T, TG, CMOS, DCVSPG and MDCVS. The design is done using DSCH 2.7f tool. Simulation and power calculation is done at different levels of technology using Microwind 2.6k Simulator. The results show the efficiency of the different design.
This paper puts forward digital circuit design using Binary Decision Diagram (BDD). BDDs can be implemented using 2:1 mux. In this paper 2T and 4T mux are used to for digital circuit design. The BDD simulation is done using CUDD-2.5.0 tool and mux implementation is done using DSCH 2.7f and Microwind 2.6k Simulator. Experiments are performed on ISCAS Benchmark Circuits at 90 nm technology. The results...
This paper puts forward a methodology for designing 1 bit full adder using a 2T mux. The 2T mux is combined in a specific manner to get a full adder with sum and carry output. The resulting 1 bit full adder is made up of 16 transistors. The simulation is done using Cadence Virtuoso Simulator using 180nm technology and 1.8V power supply. The results show the efficiency of the design.
This paper puts forward a methodology for designing 1 bit full adder using a newly proposed 4T xor gate. The 4T xor gate is formed of 2 pMOS and 2 nMOS transistors. The sum is formed using 2 xor gate and the carry is formed using a 2T mux. The resulting 1 bit full adder is made up of 10 transistors. The simulation is done using Cadence Virtuoso Simulator using 180nm technology and 1.8V power supply...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.