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A 9-bit 100 MS/s flash-successive approximation register (SAR) analog-to-digital converter (ADC), which is suitable for wireless communication systems, is presented. To reduce the active area and power consumption, front-end track-and-hold circuits in the flash ADCs are substituted by dynamic ones. A variable delay loop for enhancing dynamic performances is also included in the ADC. The prototype...
In this paper, the physical constraint effects imposed on the knee voltage along with the variation of optimum load resistance for high efficient Class-F-1 amplifier are analyzed. For the accurate analysis, the new current waveform models are identified, and the realistic approach incorporating with a non-zero knee voltage and a voltage dependent-nonlinear capacitance is employed to derive the voltage...
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