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A power-efficient 14-bit 250MS/s pipelined ADC is presented. With the aid of range-scaling technique, an original single-stage opamp is adopted to replace the conventional large-swing opamp. A novel charge compensation based (CCB) technique effectively reduces input-dependent errors of the reference voltage and it consumes no static current. Total power is reduced further because of opamp sharing,...
A low-power 14-bit 150MS/s analog- to-digital converter (ADC) is presented for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multiplying digital-to-analog converter (MDAC) and the second one reduces the total opamp power further. The dedicated sample-andhold amplifier (SHA) is removed to lower...
This paper proposes a merged first and second stage for pipelined ADC. It merges the first MDAC and second MDAC by using opamp and capacitor sharing technique to reduce power. For low supply advanced CMOS technology, the range-scaling technique is used to reduce output range in this stage, so the single-stage opamp can be used with low supply voltage to reduce power furthermore. The SHA-less technique...
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