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Soft-errors are one of the most important reliability issues in logic and memory circuits. Proper estimation of soft-error-rate (SER) is important for error mitigation and SER robust circuit design. This paper presents a physical charge collection model for accurate simulation/prediction of SER in FinFETs. The modeling is scalable and includes the effect of variation of FinFET process and layout parameters.
Investigating of ON-current boosting, short channel effect (SCE), and self-heating effect in Si pFinFET on a SiC stress relaxed buffer (SRB) layer is presented compared with SiGe pFinFET on a SiGe-SRB. Both SiC-SRB-based device and SiGe-SRB-based device show mobility boosting due to high compressive channel stress as well as enhanced SCE due to significant suppressing of subfin leakage. However, if...
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